PpgInterface.hh

#ifndef PPGINTERFACE_HH
#define PPGINTERFACE_HH
#include <stdio.h>
#include <stdlib.h>   // exit()
#include <string.h>   // memcpy()
#include <fcntl.h>    // open()
#include <unistd.h>   // close()
#include <sys/mman.h> // mmap()
#include <stdexcept>  // exceptions
#include <stdint.h>   // fixed size types
#include <string>
#include <vector>
#include <thread>
#include <atomic>
 
#define PPG_STACKDEPTH 4000 
#define PPG_MAXSEQ 100      
 
// Qsys register space is mapped into memory (above real memory)
// Address set by kernel driver?   (1G DDR3 uses 0x4000_0000 addresses)
#define ALT_STM_OFST 0xfc000000        // altera/socal/hps.h
#define ALT_LWFPGASLVS_OFST 0xff200000 // altera/socal/hps.h
 
#define HWREG_BASE (ALT_STM_OFST)
#define HWREG_SPAN (0x04000000)
#define HWREG_MASK (HWREG_SPAN - 1)
 
#define ADDR_ADJ(addr) ((long)((addr) + ALT_LWFPGASLVS_OFST) & (long)(HWREG_MASK))
 
// following are from platform-designer memory map ...
#define SYSID_QSYS_BASE 0x01000
#define PPG_BASE 0x10000
 
class MemMapException : public std::runtime_error
{
public:
  MemMapException() : std::runtime_error("MemMapException") {}
};

class PpgInterface
{
private:
  char *mmap_base;
 
  const int csr = 0x04 * 0;  
  const int test = 0x04 * 1; 
  const int addr = 0x04 * 2; 
  const int setp = 0x04 * 3; 
  const int clrp = 0x04 * 4; 
  const int dly = 0x04 * 5;  

  const int inst = 0x04 * 6;
  // const int invm = 0.04 * 7;
  const int tstamp = 0x04 * 8; 
  const int flash = 0x04 * 9;  
  // const int serial = 0x04 * 10;
  // const int modId = 0x04 * 11;
  // const int clkCtrl = 0x04 * 12
  const int gates = 0x04 * 16; 
  const int vetos = 0x04 * 17; 
 
  const int fpga_read32(int addr);       
  void fpga_write32(int addr, int data); 
  std::vector<std::string> seqstring;
  std::thread *watchthread = nullptr;
  std::atomic<bool> abort = false;
 
public:
  PpgInterface();  
  ~PpgInterface(); 
  const int ReadSysID();
  const int ReadSysTimeStamp();
  const int ReadCSR();  
  const int ReadTest(); 
  const int ReadTimeStamp();
  const int ReadGates(); 
 
  // Those registers are temporary, so cannot be read back after writing
 
  void WriteTest(int val); 
  void WriteCSR(int val);  

  void WriteStep(int index, int setpatt, int clrpatt, int delay, int instr);

  void WriteGates(uint16_t gatemask, uint8_t mode = 2); // mode: 0 = ignore gates, 1 = grandOR, 2 = grandAND
  void WriteVetos(int vetomask);  

  int LoadSeqFromFile(std::string filename, unsigned int bufindex, uint64_t &duration);
 
  const std::string GetSeqString(unsigned int i)  
  {
    if (i < seqstring.size())
      return seqstring[i];
    else
      return std::string();
  }

  void StartSeq(bool external = false);
  void Abort(); 
 
  enum state
  {
    idle,
    waiting,
    running
  };
 
  const state GetState(); 

  void TurnOffExt();
  void SetAddr(int index);  
};
 
#endif